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9268h-auto-08/14 features 8-channel hv switch interface with hv current sources linear low-drop voltage regulator, up to 80ma current capability, v cc = 5.0v 2% fulfills the oem ?hardware requirements for lin in automotive applications rev.1.3? lin master and slave operation possible supply voltage up to 40v operating voltage v s = 5v to 27v internal voltage divider for v battery sensing (2%) 16-bit serial interface (daisy-chain-capable) for configuration and diagnosis typically 8a supply current during sleep mode typically 35a supply current in active low-power mode vcc-undervoltage detection (4ms reset time) and watchdog reset logical combined at nres open drain output lin high-speed mode up to 200kbit/s adjustable watchdog timer via external resistor negative trigger input for watchdog lin physical layer complies with lin 2.1 specification and sae j2602-2 wake-up capability via lin bus and cl15 bus pin is overtemperature and short-circuit protected versus gnd and battery advanced emc and esd performance package: qfn32 5x5mm ata664151 lin system basis chip with lin transceiver, 5v regulator, watchdog, 8-channel high voltage switch interface with high voltage current sources, 16-bit spi datasheet
ata664151 [datasheet] 9268h?auto?08/14 2 1. description the atmel ? ata664151 is a system basis chip with an eight-ch annel high voltage switch interface, a lin 2.1 and saej2602-2-compliant lin transceiver, low-drop voltage re gulator, and an adjustable window watchdog. the atmel ata664151 provides 5v output voltage with up to 80ma curren t capability. this chip comb ination makes it possible to develop inexpensive, simple, yet powerful slave and master nodes for lin bus systems. the atmel ata664151 is especially designed for lin switch applications and includes almost t he entire lin node. they are designed to handle low data-rate communication in vehicles (such as in convenience electronics). improved slope control at the lin driver ensures secure data communication up to 20kbaud. sleep mode and active low-power mode guarantee mini mal current consumption even in the case of a floating bus line or a short circuit on the lin bus to gnd. figure 1-1. block diagram 16-bit serial programming interface (spi) lin physical layer interface internal supplies voltage regulator window watchdog wd-oscillator control logic int. oscillator vbatt voltage divider hv switch interface (8x) hv input cs3 cs4 cs2 cs1 lin txd rxd vs ncs vcc vbatt vdiv sck mosi miso cl15 nres ntrig wdosc iref agnd gnd cs5 cs6 cs7 cs8 nirq pwm1 pwm2 pwm3
3 ata664151 [datasheet] 9268h?auto?08/14 2. pin configuration figure 2-1. pinning qfn32, 5x5mm table 2-1. pinning pin name function 1 txd lin-bus logic data in from microcontroller 2 rxd lin-bus logic data out to microcontroller 3 nres watchdog and vcc undervoltage reset output pin (active low, open drain) 4 nirq interrupt request output to microc ontroller (active low, open drain) 5 miso spi master-in-slave-out output pin to microcontroller 6 mosi spi master-out-slave-in input pin from microcontroller 7 sck spi clock input from microcontroller 8 ncs spi chip select logic input fr om microcontroller (active low) 9 pwm1 pwm control input port from microcontroller for first cs pin group 10 pwm2 pwm control input port from microcontroller for second cs pin group 11 pwm3 pwm control input port from micr ocontroller for third cs pin group 12 wdosc connection for external resistor to set watchdog frequency 13 vdiv voltage divider output / watchdog disable input pin 14 iref reference current adjustment pin 15 cs1 high-voltage current sink/sourc e and switch i/o pin no. 1 16 cs2 high-voltage current sink/sourc e and switch i/o pin no. 2 17 cs3 high-voltage current sink/sourc e and switch i/o pin no. 3 18 cl15 wake-up on ignition high-voltage input pin 19 vbatt battery voltage input for voltage divider 20 gnd ground connection 21 lin lin-bus connection 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 31 30 29 ata664151 28 27 26 25 9 10111213141516
ata664151 [datasheet] 9268h?auto?08/14 4 22 gnd ground connection 23 gnd ground connection 24 cs4 high-voltage current source and switch i/o pin no. 4 25 cs5 high-voltage current source and switch i/o pin no. 5 26 cs6 high-voltage current source and switch i/o pin no. 6 27 cs7 high-voltage current source and switch i/o pin no. 7 28 cs8 high-voltage current source and switch i/o pin no. 8 29 vs supply input pin 30 agnd analog reference ground 31 vcc 5v voltage regulator output pin 32 ntrig watchdog trigger input from microcontroller backside gnd back side heat slug, internally connected to gnd table 2-1. pinning (continued) pin name function
5 ata664151 [datasheet] 9268h?auto?08/14 3. pin and functional description 3.1 physical layer compatibility since the lin physical layer is independent of higher lin layers (such as the li n protocol layer), all nodes with a lin physical layer as per release version 2.1 can be mixed with li n physical layer nodes found in older versions (i.e., lin 1.0, lin 1.1, lin 1.2, lin 1.3, lin 2.0 ), without any restrictions. 3.2 supply pin (vs) the operating voltage is v s = 5v to 27v. an undervoltage detection is im plemented to disable data transmission via the lin bus and the switch interface if v vs falls below v vsth in order to avoid false bus messa ges. after switching on vs, the ic starts in active mode (see also section 4.1 ?active mode? on page 9 ), with the vcc voltage regulator and the window watchdog switched on (the latter depends on the vdiv pin, see section 10. ?watchdog? on page 28 ). 3.3 ground pins gnd and agnd the ic is neutral on the lin pin in the event of gnd disco nnection. it can handle a ground shift of up to 11.5% of vs. note: please note that pin agnd is us ed for internal reference generation. this should be considered when design- ing the pcb in order to minimize the effect on the voltage thresholds. 3.4 voltage regulator output pin (vcc) the internal 5v voltage regulator is capable of driving loads up to 80ma for supplying the microcontroller and other loads on the pcb. it is protected against overloads by means of curr ent limitation and overtemperatur e shutdown. in addition, the output voltage is monitored and will cause a reset signal at the nres output pin if it drops below a defined threshold v vccthun . a safe operating area (soa) is defined for the voltage regulato r, because the power dissipation caused by this block might exceed the system?s thermal budget. 3.5 bus pin (lin) a low-side driver with internal current limitation, thermal shutdown and an internal pull-up resistor in compliance with the lin 2.1 specification are implemented. the allowed voltage r ange is from ?30v to +40v. reve rse currents from the lin bus to vs are suppressed, even in the event of gnd shifts or battery disconnection. the lin receiver thresholds are compatible with the lin protocol specification. the fa ll time from recessive to dominant bus st ate and the rise time from dominant to recessive bus state are slope-controlled. for higher bit rates the slope control can be switched off by se tting the spi-bit lsme. then the slope time of the lin falling edge is < 2s. the slope time of the rising edge strongly depend s on the capacitive load and the pull-up resistance at the lin-line. to achieve a high bit rate it is recomm ended to use a small external pull-up resistor (500 ) and a small capacitor. this allows very fast data transmission up to 200kbit/s, e. g., for electronic control tests of the ecu, microcontroller programming or data download. in this high-speed m ode a superior emc performance is not guaranteed. note: the internal pull-up resistor is only switched on in active mode and when the lin transceiver is activated by the line-bit (active mode with lin bus transceiver). 3.6 bus logic level input pin (txd) the txd pin is the microcontroller interface for controlling the st ate of the lin output. txd must be pulled to ground in order to keep the lin bus in the dominan t state. if txd is high or not connected (int ernal pull-up resistor), the lin output transisto r is turned off and the bus is in recessive state. if configured, an internal timer prevents the bus line from bei ng constantly driven in the dominant state. if txd is forced to low for longer than t dom , the lin bus driver is s witched back to recessive state. txd has to be switched to high for at least t torel to reactivate the lin bus driver (by resetting the time-out timer). as mentioned above, this time-out function can be disabled vi a the spi configuration register in order to achieve any long dominant state on the c onnected line (such as pwm transmission, or low bit rates).
ata664151 [datasheet] 9268h?auto?08/14 6 3.7 bus logic level output pin (rxd) this output pin reports the stat e of the lin bus to the microcontroller. lin high (recessive state) is reported by a high level, lin low (dominant state) is re ported by a low level at rxd. the output has push-pull characteristics meaning no external time defining measures are required. duri ng states of disabled lin- phy (configuration bit ?line? = 0), pin rxd is at high level. please note that the signal on the rxd pin is not valid for a certain period of time upon activation of the lin transcei ver (t rxdinvalid ). figure 3-1. rxd timing upon transceiver enable rxd is switched off in sleep- and unpowered mode. 3.8 cl15 pin the cl15 pin is a high-voltage input that can be used to wake up the device from sleep m ode. it is an edge-sensitive pin (low-to-high transition). thus, even if cl15 pin is at high voltage (v cl15 > v cl15th ), it is possible to s witch into sleep mode. it is usually connected to the ignition for generating a local wake-up in the application if the igni tion is switched on. the cl15 pin should be tied directly to ground if not needed. a debounce timer with a value t debcl15 of typically 160s is implemented. the pin state (cl15 on or off) can be read out through the spi interface. 3.9 reset output pin (nres) the reset output pin is an open drain ou tput and switches to low during a vcc undervoltage event or a watchdog timing window failure. please note the reset hold time of typically 4ms after the undervoltage condition has disappeared. 3.10 interrupt request output pin (nirq) the interrupt request output pin is an open dr ain output and switches to low whenever a chip-internal event occurs that is set up to trigger an interrupt. a power-up, a wake-up over lin bus, a change in a switch state or an overtemperature condition are examples of such events. the pin remains at ground until the end of the next spi command, where the interrupt source is passed to the spi master (bits irqs, see also section 7. ?serial programming interface (spi)? on page 17 ). 3.11 wdosc output pin the wdosc output pin provides a typical voltage of 1.2v intended to supply an ex ternal resistor with values between 34k and 120k. the value of the resistor and with it the pin output current adjusts the watchdog oscillator frequency to provide a certain range of time windows. if the watchdog is disabled, the output voltage is switch ed off and the pin can either be tied to vcc or left open. 3.12 ntrig input pin the ntrig input pin is the trigger input for the window watchdo g. a pull-up resistor is implemented. a falling edge triggers the watchdog. the trigger signal (low) must exceed a minimum time t trigmin to generate a watchdog trigger and avoid false triggers caused by transients. the ntrig pin should be tied directly to vcc if not needed. 3.13 vbatt input pin the vbatt is a high volta ge input pin for measurem ent purposes by means of a voltage divider. the latter provides a low- voltage signal at the vdiv pin that is linearly dependent on the input voltage. in an application with battery voltage monitoring, this pin is connected to v battery via a 51 resistor in series and a 10nf capacito r to gnd. the divider ratio is 1:4. this results in maximum output voltages on pin vdiv when reac hing 20v at the input. the vbat t pin can be tied directly to ground or left open if not needed. lin bus state 0 = dom --- 1 = rec ncs rxd x t rxdinvalid spi word with line = 1
7 ata664151 [datasheet] 9268h?auto?08/14 3.14 vdiv input/output pin this pin handles two different functions. during the vcc st artup and watchdog reset phase (pin nres driven to low), the pin acts as input and determines the setting of t he ?wdd? bit within the spi co nfiguration register (see figure 3-2 ). in other words, if the window watchdog operation shall be disabled direct ly after power-up (e.g., for microcontroller programming or debugging purposes), pin vdiv must be tied to high level until the reset phase ends (pin nres has a positive slope from low to high). in other cases, such as when pin vdiv is not driven actively by the application, the signal is assessed as low and the wdd bit (watchdog disable) is thus al so low and the window watchdog is operational (see figure 3-2 ). figure 3-2. wdd configuration bit setup during vcc startup during normal operation this pin provides a low-voltage signal for the adc such as for a microcontroller. it is sourced either by the vbatt pin or one of the switch input pins cs1 to cs8. an external ceramic capacito r is recommended for low-pass filtering of this signal. if selected in the configuration register of the spi, this pin guarantees a voltage- and temperature- stable output ratio of the selected test input and is available in all modes except sleep mode. please note that the current consumption values in the active low-power mode of atmel ? ata664151 given in the electric al characteristics lose their validity if the vdiv output pin is being used in this low-power mo de. the voltage on this pin is actively clamped to vcc if the input value would lead to higher values. 3.15 iref output pin this pin is the connection for an external resistor towards gr ound. it provides a regulated vo ltage which will cause a resistor - dependent current used as reference for the current sources in t he switch interface i/o ports. the resistor should be placed closely to the pin without any additional capacitor. a fail-safe circuitry detects if the resistor is missing or if there is a short towards ground or vcc on this pin. an internal fail-s afe current is generated in this event. please see also section 8. ?switch interface unit? on page 22 for further details. 3.16 cs1 to cs8 high-voltage input/output pins these pins are intended for contact monito ring and/or constant current sourcing. a total of eight i/os (pins cs1 through cs8) are available, of which three (cs1, cs2 and cs3) can be configured either as current sources (such as for switches towards ground) or as current sinks (such as for switches to wards battery). the other five pins (cs4 to cs8) have only current sourcing capability. apart from a hi gh voltage (hv) comparator for simple s witches, the i/os are also equipped with a voltage divider to enable analog voltage measurements on hv pins by using the adc of the application?s microcontroller (see section 3.14 ?vdiv input/output pin? on page 7 for further details). also, each input can trigger an interrupt upon state change even during active low-power mode. if one or more csx pi ns are not needed, can be left open or directly connected to vs. note: unused csx-pins should be connected directly to vs. 3.17 pwm1..3 input pins these pins can be used to control the switch interface current sources directly, such as for pulse width-modulated load control or for pulsed switch scanning. th ey accept logic level signals from the microcontroller and are equipped with pull- down structures so in case of an open connection , the input is well defined. for more information see section 8. ?switch interface unit? on page 22 . the assignment of the current sources to the three pwm input pins is described in section 8.1 ?current sources? on page 22 . nres vdiv (driven externally) wdd config bit state logic level a logic level a z (high imp.) x low from vcc startup
ata664151 [datasheet] 9268h?auto?08/14 8 4. operating modes there are two primary modes of op eration available with the atmel ? ata664151. active mode: in this mode the vcc voltage regulator is active and the spi is ready for operation. in addition, all other peripherals can be enabled or disabled by configuration via spi. af ter power-up the watchdog is enabled (dependent on the vdiv pin only, see section 3.14 ?vdiv input/output pin? on page 7 ), whereas the lin transceive r and the switch interface unit are switched off. sleep mode: all peripherals are switched off (including the vcc voltage regulator), a wake-up is only possible via the lin bus or the cl15 pin. in this mode the ic has the lowest possible current consumption. figure 4-1. state diagram unpowered mode all circuitry off config init load wdd bit dependent on vdiv input level active mode vcc: on all other peripherals config dependent sleep mode vcc: off all other peripherals: off v vs < 3.3v v vs < 3.3v v vs < 3.3v v vs > 3.5v sleep bit = 1 lin wake up or cl15 wake up
9 ata664151 [datasheet] 9268h?auto?08/14 4.1 active mode if sufficient voltage is applied to the ic at the vs pin, the configuration register is initialized and the chip changes to act ive mode. in this mode different states of power consumption are possible, depending on the configuration selected for the chip and activity on the spi. the following table lists all power states (except unpowered) for the atmel ? ata664151. the descriptions in brackets below the peripherals refer to th e configuration register of at mel ata664151, accessible via spi. please note that the table above only lists the active mode stat es with just one extra peripheral enabled. except for active low-power, any combination of t he states above and thus also the current consumption is possi ble - for example, the parallel operation of the lin bus transceiver and th e current sources. the required supply cu rrent is then at least the sum of the values given above. table 4-1. state and current consumption vs. enabled periphery state and vs pin current consumption lin bus transceiver voltage divider vcc voltage regulator watchdog spi data comm. current sources sleep i vs = i vssleep off off off off off off active low-power i vs = i vsact_lp off (line=0) off (vdive=0) on off (wdd=1) off (ncs=1) off or standby (csex=x and cscx=0 and pwmy=0) active spi comm. i vs = i vsact_spi off (line=0) off (vdive=0) on off (wdd=1) on (ncs=0) off (csex=0) active with watchdog i vs = i vsact_wd off (line=0) off (vdive=0) on on (wdd=0) do not care off (csex=0) active with lin-bus transceiver i vs = i vsact_lin on (line=1) off (vdive=0) on off (wdd=1) do not care off (csex=0) active with current sources i vs = i vsact_cs off (line=0) off (vdive=0) on off (wdd=1) do not care on (csex=1 and (cscx=1 or pwmy=1)) active with voltage divider i vs = i act_vdiv off (line=0) on (vdive=1) on off (wdd=1) do not care off (csex=0) note: legend: 0 = bit is programmed 0 1 = bit is programmed 1, x = disregards
ata664151 [datasheet] 9268h?auto?08/14 10 4.2 sleep mode this mode must be initialized via the spi configuration regist er. all peripherals, i.e., the li n transceiver, the watchdog, the voltage dividers, the switch interface unit and the vcc voltage regulator are switched off. the overall supply current on pin vs is then reduced to a minimum. two wake-up mechanisms are possible to leave sleep mode again: wake-up via lin and wake-up via cl15. 4.2.1 wake-up from sleep mode via lin a voltage below the lin pre-wake threshold on the lin pin activates a wake-up detection phase. a falling edge at the lin pin followed by a dominant bu s level maintained for a time period of at least t bus and the following rising edge at the lin pin (see figure 4-2 ) results in a remote wake -up request. the device switches from sleep mode to active-low power mode (vcc regulator enabled), but the lin tran sceiver is still deactivated. only the internal lin slave termination resistor is switched on. the remote wake-up request is indicated by a low level at the nirq pin to interrupt the microcontroller (see figure 4-2 ). in addition, the wake-up source is stated in the chip status register which can be read out via spi. configuring the chip via spi must be used to en able the lin transceiver and allow data to be send and/or transmitted via the lin bus. note that this can only be done after the low level at the nres pin has been eliminated (after vcc ramp-up and the stabilization phase). figure 4-2. lin wake-up from sleep mode with the initialization of the confi guration register by the microcontr oller, the status word of atmel ? ata664151 is transmitted back, including the wake-up source. in other words, the two stat us bits ?irqs1? and ?irqs0? both read back as '1'. for more information see section 7. ?serial programming interface (spi)? on page 17 . lin bus vcc nres nirq spi comm. watchdog state init ic/ read status start watchdog lead time watchdog off vcc startup t bus = 90s typ t nres = 4ms typ
11 ata664151 [datasheet] 9268h?auto?08/14 4.2.2 wake-up from sleep mode via cl15 voltage above v cl15h at pin cl15 activates a cl15 wake-up detection phase. this state must persist for at least t cldeb in order to detect a wake-up. if the pulse is too short, the ic remains in sleep mode. when leaving sleep mode first the vcc voltage regulator is acti vated to enable the microcontroller supply. then as soon as the vcc level reaches valid levels, the vcc startup timer is star ted. during this time, the nres pin is kept low in order to keep the microcontroller from running. this ensures a proper voltage supply and signal stabilization in the application. with the rising edge at nres, the spi is r eady for communication and the atmel ? ata664151 can be initialized. figure 4-3. cl15 wake-up from sleep mode the wake-up behavior is analogous to a wake-up via the lin bus as seen above. one difference is that no negative edge is required to start the wake-up procedure as is the ca se for lin wake-ups. after the vcc startup time t wdnres has elapsed, nres is released and therefore pulled up, either by the internal or additional external resistors. the microcontroller can then configure the atmel ata664151 and thus be no tified about the actual status includ ing the wake-up source. here, the two status bits ?irqs1? and ?irqs0? read back as '10'. cl15 vcc nres nirq spi comm. watchdog state init ic/ read status start watchdog lead time watchdog off vcc startup t cl15deb = 160s typ t nres = 4ms typ
ata664151 [datasheet] 9268h?auto?08/14 12 4.2.3 sleep mode: behavior at a floating lin bus or a short-circuited lin to gnd in sleep mode the device has very low current consumption even durin g short-circuits or floating conditions on the bus. a floating bus can arise if the mast er pull-up resistor is missing, such as when it is switched off while the lin master is in sl eep mode or even if the power supply of the master node is switched off. in order to minimize the current consumption i vs in sleep mode during voltage levels on the lin pin below the lin pre-wake threshold, the receiver is activated only for a specific time t mon . if t mon elapses while the voltage at the bus is lower than pre-wake detection low (v linl ) or higher than the lin dominant level, the receiver is switched off again and the circuit changes back to sleep mode. the current consumption is then i vssleep_short (typ. 10a more than i vssleep ). if a dominant state is reached on the bus, no wake-up occurs. even if the voltage rises above the pre-wake detection high (v linh ), the ic will stay in sleep mode. this means the lin bus must be above the pre-wake detection threshold v linh for a few microseconds before a new lin wake-up is possible. figure 4-4. floating lin bus during sleep mode if the atmel ? ata664151 is in sleep mode and the voltage le vel at the lin bus is in dominant state (v lin < v busdom ) for a period exceeding t mon (during a short circuit at lin, for example) , the ic switches back to sleep mode. the v s current consumption is then i vssleep_short (typ. 10a more than i vssleep ). after a positive edge at the lin pin the ic switches directly to active mode. i vssleep i vssleep i vsfail i vssleep_short v busdom v linl i vs t mon lin pre-wake lin dominant state lin bus mode of operation int. pull-up resistor rlin wake-up detection phase off (disabled) sleep mode sleep mode
13 ata664151 [datasheet] 9268h?auto?08/14 figure 4-5. short circuit to gnd on the lin bus during sleep mode 4.3 active low-power mode in this mode, the vcc voltage regulator is active and can therefore supply the application?s microcontroller. all other functions of the atmel ? ata664151 are disabled in the configuration regi ster respectively inhibited by the pwm pins for the csx pin current sources. this reduces the current consum ption of the chip itself to a low-power range of typically below 50a. note that this is only valid if the chip select input of the spi, ncs, is al so kept at a high level. if it is pulle d to ground, spi communication is enabled, causing a higher current consumption. if the lin transceiver is disabled, the bus is monitored for a wake-up event, initialized with a voltage level below the lin pre-wake threshold at the lin pin. sleep mode i vssleep i vsfail i vssleep_short v busdom v linl lin pre-wake lin dominant state lin bus i vs mode of operation int. pull-up resistor rlin off (disabled) on (enabled) wake-up detection phase sleep mode active mode t mon t mon
ata664151 [datasheet] 9268h?auto?08/14 14 figure 4-6. lin wake-up from active low-power mode the negative edge on the nirq pin indicates a change of cond itions, in this case a wake-u p request at the lin bus. the microcontroller can check the irq source by assessing the ?irqs1 ? and ?irqs0? bits in the stat us register. note that if a watchdog operation is desired, it must be enabled via the configuration register. the behavior can be transferred to a wake-up over cl15 pin from active low-power mode. figure 4-7. cl15 wake-up from active low-power mode apart from the lin transceiver and the cl15 input, the high-vo ltage i/o ports cs1 to cs8 can also be used to generate interrupts while in active low-power mode. this can be done by enabling the current sources so that they can generate an interrupt with the corresponding csex- and csiex bits in the co nfiguration register. as long as the current source is not enabled (cscx='0' and pwmy low), the ic stays in active low-po wer mode (if all other conditions are met, such as disabled watchdog). the pwmy pin has to be set to high by the microcont roller, for example, controlled via a pwm timer unit, in order to check the condition of the connected switch. because the sw itch interface unit is enabled, current consumption increases drastically. this ?switch scanning phase? can be short com pared to the interceding idle time so the mean current consumption of the ic remains close to the active low-power mode current c onsumption. for more information, see section 8.1 ?current sources? on page 22 and section 8.2 ?switch inputs? on page 24 for further details. lin bus vcc nres nirq spi comm. watchdog state enable wd/ read status start watchdog lead time watchdog off t bus = 90s typ cl15 vcc nres nirq spi comm. watchdog state enable wd/ read status start watchdog lead time watchdog off t cl15deb = 160s typ
15 ata664151 [datasheet] 9268h?auto?08/14 4.4 behavior under low supply voltage conditions when connected to the car battery, the voltage at the vs pin increases according to the blocking capacitor (see figure 4-8 ). as soon as v vs exceeds its undervoltage threshold v vstho , the switch interface unit and the lin transceiver can be used. the ic is in active mode after power-up with the vcc vo ltage regulator and the window watchdog enabled ? the latter depends on the state of the pin vdiv. the vcc out put voltage reaches its nominal value after t vcc . this time depends on the externally applied vcc capacitor and the load. the nres is low for the reset time delay t reset . during this time t reset , no spi communication and thus no configuration changes or status checks are possible. figure 4-8. vcc versus vs please note that upper graph is only valid if the vs ramp -up time is much slower t han the vcc ramp-up time t vcc and the nres delay time t reset . if during active mode the voltage level of vs dr ops below the undervoltage detection threshold v vsthu , an interrupt is indicated to the microcontroller by means of a low-signal at the nirq pin. furt hermore, both the switch interface unit and the lin transceiver are shut down in order to avoid malfunctions or false bus messages. this shutdown is achieved by simply inhibiting the functions internally. the corresponding bits in the configuration register ar e not cleared. this means the functionality resumes if enabled after the supply voltage exceeds above v vstho again. if during sleep mode the voltage level of vs dr ops below the undervoltage detection threshold v vsthu , no change of mode or any other activity by the atmel ? ata664151 occurs as long as the level does not drop below the minimum operation value v vsopmin . vs in v v in v 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 regulator drop voltage v d nres vcc vs lin 6.5 7.0 6.5 7.0
ata664151 [datasheet] 9268h?auto?08/14 16 5. wake-up scenarios from sleep mode 5.1 remote wake-up via the lin bus a voltage lower than the lin pre-wake detection v linl at the lin pin activates the internal lin receiver. a falling edge at the lin pin followed by a dominant bus level v busdom of at least t bus and a rising edge at pin lin results in a remote wake-up request. the device swit ches from sleep mode to active mode. th e vcc voltage regulator is activated and the internal slave termination resistor is switched on. the remote wake-up request is indicated by a low level at the nirq pin. this generates an interrupt for the microcon troller and a corresponding flag in the spi register. 5.2 local wake-up via pin cl15 a positive edge at pin cl15 followed by a high voltage level for a given time period (> t cl15deb ) results in a local wake-up request. the device switches to active mode. the debouncing time ensures that no transien ts at cl15 create a wake-up. the local wake-up request is indicated by a low level at the nirq pin, generating an interrupt for the microcontroller. during high-level voltage at the cl15 pin, it is possible to switch to sleep mode via an spi command. in this case the voltage at the cl15 pin has to be switched to low for at least t cl15deb before the positive edge at this pin starts a new local wake-up request. note that this time can be extended by adapting the external circuitry. 5.3 wake-up source recognition the device can distinguish between different wake-up sources. the source for the wake-up event can be re ad out of the spi diagnosis register. 6. wake-up scenarios from active low-power mode generally the active low-power mode is only possible if al l clock-dependent peripherals such as the lin transceiver and the watchdog are disabled. in addition, no spi communication is allowed to take place to minimize current consumption. 6.1 wake-up from csx pins the switch input pins can each be used to generate an interrupt request while in active low-power mode. a state change detection circuitry is implement ed for this functionality (see section 8.2 ?switch inputs? on page 24 ). for this functionality, the respective current source needs to be config ured so that it is controlled via the dedi cated pwmy pin. a rising edge on this pin enables the current source, allowing a stable switch readback si gnal to be delivered at the csx pin. the switch state is updated with a falling edge at the pwmy pin. if a change of state is monitored, an in terrupt request is generated if the csie bit of the affected current source is set to '1' in the config uration register. if no wake-up should occur on a certain switch - either because there is no application demand for this or a fa ilure such as a hanging switch or a connection line short-circuit is present - it can be prevented by disabling the current source in the spi configuration register. 6.2 wake-up from lin bus if during active low-power mode (i.e., t he lin transceiver is disabled) the lin b us is tied to ground for at least t bus . this wake-up request is indicated by a negative edge at the nirq pin. please note that the atmel ? ata664151 stays in active low-power mode for as long as no spi communication occurs or configuration changes are made. current consumption is only higher during the lin bus assessment, in other words as long as the voltage on the lin bus is below v lin,prel . regardless of the lin bus state, th is assessment phase ends after t lin_wudet at the latest. this ensures a low current consumption even during shorts on the lin bus or when there are floating bus levels. 6.3 wake-up from cl15 if during active low-power mode the voltage on the cl15 pin exceeds v cl15h for at least t cl15deb , an interrupt request is triggered to indicate a change of state at th e cl15 pin. please note that after the t cl15deb has elapsed, the atmel ata664151 stays in active low-power mode for as long as no sp i communication occurs or configuration changes are made.
17 ata664151 [datasheet] 9268h?auto?08/14 6.4 wake-up from spi if during active low-power mode the chip select input ncs is tied to ground, atmel ? ata664151 leaves the active low-power mode in order to complete a data communication with the spi master. the operating mode of the ic is adapted in accordance with the configuration register update. if no change in configuration has taken place ? for example, because only the actual status was polled or another bus member connec ted via daisy chaining was addressed ? atmel ata664151 goes back to active low-power mode as soon as ncs returns to high level. 7. serial programming interface (spi) most features of the ic are configured via spi. diagnostics are carried out using this interface also. it can be used in active mode as long as there is no undervoltage condition at the vcc pin. the atmel ata664151 spi features both pol = 0 / pha = 0 and pol = 1 / pha = 1 operating modes. figure 7-1. pol = 0 / pha = 0 setup figure 7-2. pol = 1 / pha = 1 setup the interface contains four pins. ncs (chip select pin, active low) sck (serial data clock) mosi (master-out-slave-in serial data port input from master) miso (master-in-slave-out serial data port output from sbc; this pin is tri-state if ncs is high) no data is loaded from mosi on sck edges or provided at miso if chip select is not active. the output pin miso is not actively driven (tri-sta te) during these phases. ncs sample setup msb x z 14 13 12 2 1 x x lsb msb 14 13 12 2 1 z mosi msb lsb mosi sck miso ncs setup sample x x msb 14 13 3 2 lsb x 1 x z msb 14 13 3 2 lsb x 1 mosi sck miso
ata664151 [datasheet] 9268h?auto?08/14 18 the data transfer scheme (bit order) is ms b first, meaning the first bit that is transf erred is the most significant bit of the register, with the transfer ending with the least significant bit. these bits are listed on the next pages. the mosi bits 15 to 0 refer to the configuration register. this means the configurat ion register is updated with each spi communication. at the same time the miso word is built from the status register bits 15 to 0. note that changes in the configuration are only visible in the next status query. this means, fo r example, that if you enable the watch dog with an spi command, the status ?watchdog active? is not reported in this data transmission but in the next one. in order to load any data into the chip, the chip select signal must be removed (i.e., set to high) after the 16 sck clock periods. a minimum data evaluation time t spieval,min has to transpire before the next data transfer can start. please note also that any change in configuration of the ic requires this time to go into effect. figure 7-3. spi configuration timing the following table lists the bits of the configuration register in the atmel ? ata664151. table 7-1. spi configuration register # bit name description default ( ' 0 ' ) programmed with ' 1 ' remark 15 msb lsme enable lin-bus high-speed mode normal high-speed see lin transceiver description 14 tttd disable txd time-out timer enabled disabled see section 3.6 ?bus logic level input pin (txd)? on page 5 13 imul iref multiplier value x100 x50 see section 8. ?switch interface unit? on page 22 12 line enable lin transceiver disabled enabled see lin transceiver description 11 sleep go to sleep stay in active mode enable sleep mode see section 4. ?operating modes? on page 8 10 vdive enable vdiv as output vdiv off (high-ohmic) vdiv on (selected voltage divider active) see section 8.2.2 on page 26 and section 8. ?switch interface unit? on page 22 9 vdivp programming vdiv output source vdiv shows vbatt divider vdiv shows one cs divider output see section 8.2.2 on page 26 and section 8. ?switch interface unit? on page 22 ncs mosi data chip configuration config data new config t spieval_min previous config
19 ata664151 [datasheet] 9268h?auto?08/14 8 cspe enable switch interface unit programming disabled enabled see section 8. ?switch interface unit? on page 22 7 csa2 address bit 2 (msb) for switch input 0 1 used as selector for vdiv and for programming of one current source 6 csa1 address bit 1 for switch input 0 1 used as selector for vdiv and for programming of one current source 5 csa0 address bit 0 (lsb) for switch input 0 1 used as selector for vdiv and for programming of one current source 4 cse enable addressed current source disabled enabled see section 8. ?switch interface unit? on page 22 3 csssm switch between source/sink mode source mode selected (highside) sink mode selected (lowside) sink mode is only possible for switch interfaces 1-3 2 csc control of addressed current source external (cse and pwmy) internal (cse only) see section 8. ?switch interface unit? on page 22 1 csie (cspe=1) enable interrupt from addressed switch input disabled enabled csie will be altered if cspe of the spi word is '1'. see section 8. ?switch interface unit? on page 22 csscd (cspe=0) cs port current source slope control enabled disabled csscd will be altered if cspe of the spi word is '0'. see section 8. ?switch interface unit? on page 22 0 lsb wdd disable watchdog enabled (if pin vdiv on low level) disabled see section 10. ?watchdog? on page 28 table 7-1. spi configuration register (continued) # bit name description default ( ' 0 ' ) programmed with ' 1 ' remark
ata664151 [datasheet] 9268h?auto?08/14 20 the following table lists the bits of the status register in atmel ? ata664151. figure 7-4. spi status register # bit name description result = "0" result = "1" remark 15 msb otvcc (vdive=0) overtemperature prewarning from vcc regulator temp sensor temperature not critical temperature critical see section 9. on page 27 ; only valid if vdive of prev. command was '0' mvbatt (vdive=1) vbatt voltage monitor vbatt not visible on vdiv vbatt visible on vdiv only valid if vdive of prev. command was '1' 14 otlin (vdive=0) overtemperature signal from lin driver temp sensor no over- temperature over- temperature see section 3.5 on page 5 ; only valid if vdive of prev. command was '0' mrdiv2 (vdive=1) cs port voltage monitor, address bit 2 (msb) mrdiv2..0 indicate the address of the cs port volt. monitor visible on vdiv this bit is only shown if vdive of previous command was '1' 13 otcs (vdive=0) overtemperature signal from current sources temp sensor no over- temperature over- temperature see section 8. on page 22 ; only valid if vdive of prev. command was '0' mrdiv1 (vdive=1) cs port voltage monitor, address bit 1 mrdiv2..0 indicate the address of the cs port volt. monitor visible on vdiv this bit is only shown if vdive of previous command was '1' 12 cl15s (vdive=0) cl15 pin status v cl15 < v cl15h v cl15 v cl15h see section 11. on page 30 ; only valid if vdive of prev. command was '0' mrdiv0 (vdive=1) cs port voltage monitor, address bit 0 (lsb) mrdiv2..0 indicate the address of the cs port volt. monitor visible on vdiv this bit is only shown if vdive of previous command was '1' 11 wds watchdog status watchdog disabled watchdog enabled see section 10. ?watchdog? on page 28 10 vss vs voltage level status vs voltage ok vs undervoltage see section 4.4 on page 15 9 irqs1 interrupt request source ?00? powerup ?01? cs change ?10? cl15 wake-up ?11? lin wake-up information will be cleared after status register readout via spi 8 irqs0 7 cs8cs switch interface 8 comparator status v cs8 < v csxth v cs8 > v csxth see section 8. ?switch interface unit? on page 22 6 cs7cs switch interface 7 comparator status v cs7 < v csxth v cs7 > v csxth see section 8. ?switch interface unit? on page 22 5 cs6cs switch interface 6 comparator status v cs6 < v csxth v cs6 > v csxth see section 8. ?switch interface unit? on page 22
21 ata664151 [datasheet] 9268h?auto?08/14 the spi is capable of daisy chaining as well. in other words, if other ics with a daisy-chaining-enabled spi are to be used in the application, they can simply be in terconnected one af ter the other (see figure 7-5 ). figure 7-5. daisy chaining configuration it can be seen that th e data output of atmel ? ata664151 is not connected to the data input of the master but of another spi member which is also capable of daisy chaining. in order to transmit data, the microcontroller has to send the sum of clock pulses for all bus members. in the example above, if the other spi member also features 16 bits, the microcontroller has to perform 32 clock cycles with ncs ke pt low to completely move the data. the first 16 bits of such a transmission are initially fed into the atmel ata664151. but when ncs stays low, the dat a is not loaded into its confi guration register but instead shifted out again with the next 16 bits. at the same time the status register of at mel ata664151 is first fed into the other spi bus member which then needs to transfer the data over to the microcontroller with the second 16 bits. in summary, the daisy chaining is one way to have multiple bus members connected to a single master. because not all devices support these o perating modes, the atme l ata664151 still supports the direct a ddressing mode using the ncs pin. if ncs is not pulled to ground, all data traffic on the spi is disregarded by the atmel ata664151. 4 cs5cs switch interface 5 comparator status v cs5 < v csxth v cs5 > v csxth see section 8. ?switch interface unit? on page 22 3 cs4cs switch interface 4 comparator status v cs4 < v csxth v cs4 > v csxth see section 8. ?switch interface unit? on page 22 2 cs3cs switch interface 3 comparator status v cs3 < v csxth v cs3 > v csxth see section 8. ?switch interface unit? on page 22 1 cs2cs switch interface 2 comparator status v cs2 < v csxth v cs2 > v csxth see section 8. ?switch interface unit? on page 22 0 lsb cs1cs switch interface 1 comparator status v cs1 < v csxth v cs1 > v csxth see section 8. ?switch interface unit? on page 22 figure 7-4. spi status register # bit name description result = "0" result = "1" remark ata664151 ncs sck mosi miso microcontroller ncs sck mosi miso other spi member ncs sck mosi miso
ata664151 [datasheet] 9268h?auto?08/14 22 8. switch interface unit a total of eight high-side current sources with high voltage comparators and voltage dividers are available for switch scanning or for example, led driving pur poses. note that three of them (cs1, cs2, and cs3) can also be switched to low-side current sinks in the configuration register via the spi. system wake-up from active low-power mode is possible through state change monitoring. please see figure 8-1 for an overview of the interface structure. figure 8-1. principle schematic of a high -side-only switch interface (cs4 - cs5) the control signals cse and csc are conf iguration register bits, and unique for eac h of the eight interfaces. the output signal dout_cs of the comparator can be probed via the spi status register bit csxcs. 8.1 current sources the current sources are available in active mode. they delive r a current level derived from a reference value measured at the iref pin. this pin is voltage-stabilized (v iref = 1.23v typ.) so that the reference current is directly dependent on the externally applied resistor connected between iref pin and ground. the resulting current at the csx- pins is (1.23v/r iref ) ri cs . for example, with a 12k resistor between iref and gnd the value of the current at the csx-pins is 10ma (assumed imul = '0' => ri cs_h = 100). for fail-safe reasons, both a missing an d a short-circuited resistor are detected. in this case, an internally generated reference current i ireffs is used instead to maintain a certain functionality. the current sources of i/os 1-3 (cs1..cs3) can be configured ei ther as high-sides (current so urces) or low-sides (current sinks). this selection is done by the csssm bit of the configur ation register. the default val ue of '0' enables the high-side source whereas a '1' enables the low-side sink. the output current level can be divided by 2 with the imul bit in the configuration regist er. with the default setting of imul = '0', the ratio between the output current i csx and the reference current i iref is ri cs_h (typ. 100). if set to '1', the ratio reduces to ri cs_l (typ. 50). state change detector agnd i iref rl cs v csxth (4v dc) mux hv comp vs pwmy csx vdiv d_statechange dout_cs_x csa [2..0] vdivp vdive cse [1..8] csc [1..8] vbatt 3r r
23 ata664151 [datasheet] 9268h?auto?08/14 if a current source is enabled by the c onfiguration register (set to ready state, bit cse = '1'), it supports two different operating modes. directly controlled by the confi guration register - bit csc = '1' externally gated (inhibited with the pwmy pin) - bit csc = '0' (default) these modes can be selected independently fo r each current source via the configurat ion register. while the current source is permanently on with csc = '1' it is c ontrolled externally by the logic level i nput pins pwmy with csc = '0' for switch scanning or led driving (external pwm control). the following truth table summarizes all setup variants. please see table 8-2 for the assignment between the three available pwm control ports pwm1..3 and the eight current source outputs cs1..8. there is one common control bit for all curr ent sources, the bit ?csscd?. with this bit, the slope control of all eight sources can be disabled. by default, the slope control is activated a nd all currents are switched on and off smoothly (see also parameter du csx,rise and du csx,fall ). when setting this bit to '1', the current sources are enabled and disabled without transition times. table 8-1. cs port configuration table csex cscx csssm pwmy cs1..3 cs4..8 active low-power mode possible 0 x x x off off yes 1 0 x 0 off off yes 1 1 0 x 1 1 no 1 1 1 x 0 1 no 1 0 0 1 1 1 no 1 0 1 1 0 1 no legend: 0 -> bit = '0' for csex, cscx and csssm; logic lo w for pwmy; ls current source active for cs1..3 1 -> bit = '1' for csex, cscx and csssm; logic high for pwmy; hs current s ource active for cs1..8 x -> do not care for csex, cscx, cssm and pwmy off -> current source disabled table 8-2. assignment of current sources to the pwmy ports pwm port cs1 cs2 cs3 cs4 cs5 cs6 cs7 cs8 pwm1 x - - - - - x x pwm2 - x - - x x - - pwm3 - - x x - - - -
ata664151 [datasheet] 9268h?auto?08/14 24 in order to change the configuration of a certain current source via spi, it must be addressed and the current source programming bit cspe must be set to '1'. please see table 8-3 for the eight available current sources. that is, if any of the followi ng configuration bits (cse, csssm , csie, and csc) of a certain i/o port shall be changed, the required data word for the spi must contain the desired i/o number (bits csa0..2) and the programming enable bit cspe must be '1'. only in this case, the corresponding bits in the spi data word are loaded into the configuration register of the selected switch interface. for the glo bal current source configuration bit csscd (slope control for current sources), the cspe bit must be '0' in order to be changed via an spi command. that is, either the four indivi dual configuration bits (cse, csssm, csie and csc) or the global configuration bit (csscd) can be changed with one spi command word. dependent on the selected current, the supply voltage, the ex ternally applied load and the number of current sources activated, a not neglectable amount of power will be dissipated in atmel ? ata664151. in order to protect the ic from damage, the current sources are equipped with thermal monitors. if the temperatur e in one of the monitors exceeds t jsd , all current sources will be shut down and an interrupt will be gene rated. note that th e current source enabled bits (cse) in the configuration register are not cleared by this event. that is, the curr ent sources will be enabled after a certain cooling time . 8.2 switch inputs 8.2.1 voltage comparators each switch input has a high voltage co mparator, a state-c hange-detection register for wake-up and interrupt request generation and a voltage divider with a low-voltage output that can be fed th rough to the measurement pin vdiv. in sleep mode, the hv comparat ors and the voltage dividers of each input are switched off. in active mode, the comparator of a channel is activated together with it s current source. it has a threshold of v csxth . the output signal dout_csx of the comparator is debounced with a delay of t csdeb . a voltage above the threshold will generat e a logical '1' in the status register bit csxcs whereas a voltage below will lead to a '0'. the comparator output signal is also fed into a state change detection logic t hat can be used to generate wake-up events in form of an interrupt request, si gnalized on pin nirq. please see figure 8-2 on page 25 for an overview of the state change detection unit. table 8-3. cs port addressing table current source on pin bit csa0 bit csa1 bit csa2 cs1, high- or lowside 0 0 0 cs2, high- or lowside 1 0 0 cs3, high- or lowside 0 1 0 cs4, highside only 1 1 0 cs5, highside only 0 0 1 cs6, highside only 1 0 1 cs7, highside only 0 1 1 cs8, highside only 1 1 1
25 ata664151 [datasheet] 9268h?auto?08/14 figure 8-2. state change detection circuitry as can be seen in figure 8-2 , the data from the comparator is latched with the falling edge of either the pwmy pin or the csc bit. that is, the data is latched in the same moment when the current source is switched off. this ensures that the comparator signal was already stable when its output is evaluated. the output signal d_st atechange is evaluated by the main control logic. if the interrupt enable bit csie is set in the configuration register and d_s tatechange is '1', an interrup t is generated and reported by a low level on pin nirq. please see figure 8-3 for an example of the state change detection system. figure 8-3. interrupt generation upon state change the output state of the hv comparator is sampled with each falling edge of th e pwmy or csc signal. as soon as the sampled state changes, an interrupt request is given. in order to have minimum power consumption also for switch scanning applications, atmel ? ata664151 is able to switch to active low-power mode even if current sources are enabled with the csex bit in the configuration register. as long as the current source is inhibited (for example, by having cscx programmed to 0 and pwmy also at low level), the ic can be in active low-power mode (dependent on the other peripherals, see also table 4-1 on page 9 ). the current source is then in a kind of stand-by situation. as soon as the pwmy pin is rais ed, the ic switches to active mode with the defined current sources on. v csxth (4v vdc) d r d-ff q d dout_cs d_statechange_x r d-ff q csx csc_x cse_x pwmy hv comp cse pwmy/ csc csx nirq sampled state dout_cs_x d_statechange_x t nirqtrig t csdeb signal sample point signal sample point
ata664151 [datasheet] 9268h?auto?08/14 26 8.2.2 voltage dividers a voltage divider (division by 4) is included for each of the eight cs port channels. please note that the divider is always referred to local ground (pin agnd), regardless of the respective current source/sink configurat ion. as there is only one output available for all voltage dividers of the chip, only one of them can be active at a time . the spi data word must contain the following information in order to activate th e voltage divider of a certain switch interface. the voltage divider enable bit vdive must be '1'. the vdiv programming source bit vdivp must be '1'. the desired channel must be coded in the three address bits csa0..2. please see table 8-4 for a list of all voltage divider programming i nputs and their corresponding vdiv output state. table 8-4. voltage divider addressing table vdive vdivp csa2 csa1 csa0 vdiv 0 x x x x off 1 0 x x x vbatt / 4 1 1 0 0 0 cs1 / 4 1 1 0 0 1 cs2 / 4 1 1 0 1 0 cs3 / 4 1 1 0 1 1 cs4 / 4 1 1 1 0 0 cs5 / 4 1 1 1 0 1 cs6 / 4 1 1 1 1 0 cs7 / 4 1 1 1 1 1 cs8 / 4 legend: 0 -> bit = '0' 1 -> bit = '1' x -> do not care
27 ata664151 [datasheet] 9268h?auto?08/14 9. voltage regulator the vcc voltage regulator in atmel ? ata664151 is a linear low-drop regulator and requires an external capacitor for compensation and for smoothing the disturbances in the microcon troller. it is mandatory to use a capacitor with c > 1.8f and esr of below 5 . an additional ceramic capacitor with c = 100nf is recommended for emi suppression. the values of these capacitors can be varied depending on the application. figure 9-1. vcc voltage regulator: ramp-up and undervoltage detection the vcc output transistor is contributing to the ics total powe r dissipation ? defined by the voltage drop over the transistor and the output current i vcc . in the figure below , the safe operating area of atmel ata664151 is shown. to avoid a thermal shutdown of the vcc output, th e maximum load current decreases with rising ambient temperature and/or battery supply voltage. please note also that the curren t sources contribute to power dissipation. figure 9-2. power dissipation: safe operating area (soa ) of vcc output current versus supply voltages vs at different ambient temperatures, rthja = 40k/ w and no current source (pins csx) active nres 5v vcc t t t vs 5v v thun t res_f t reset t vcc 5.5v 12v 90 80 70 60 50 40 30 20 10 0 output current (ma) 4 6 8 1012 1416 182022 2426 28 vs [v] (v_vcc = 5v) ta = 85c ta = 105c ta = 125c
ata664151 [datasheet] 9268h?auto?08/14 28 because the vcc voltage generation is usually fundamental to system operatio n, there is a thermal prewarning implemented in the atmel ? ata664151. the thermal monitor of the vcc output transistor can indicate a critical temperature condition of t vccprew by means of an interrupt and the status bit otvcc in the status register of th e chip. the microcontroller can thus react to these events by shut ting down external loads that use the vcc or reducing its own power consumption in order to avoid a thermal shutdown. nevertheless, if the junction temperature of the output transistor exceeds the shutdown threshold t jsd , the transistor as well as the vcc are shut down until the te mperature has decreased at least by t jsdhyst . after this cooling-down period, the regulator starts again in the same way as when powering up or for a wake-up from sleep mode. for microcontroller programming, it may be necessary to supply the vcc output via an external power supply. it is then mandatory to disconnect pin vs of the system basis ch ip, and an operation of atmel ata664151 is not possible. 10. watchdog the watchdog expects a trigger signal from the microcontrolle r at the ntrig (negative edge) input within a time window of t wd . the trigger signal must exceed a minimum time t trigmin > 7s. if a triggering signal is not received, a reset signal will be generated at output nres. the timing basis of the watchdog is provided by the internal watchdog oscillator. its time period, t wdosc , is adjustable via the external resistor r wd_osc (34k to 120k ). during sleep mode the watchdog is switched off to reduce current consumption. in order to ent er active low-power mode, the watchdog also needs to be disabled via the configuration r egister. in order to avoid false watchdog disabling, this configuration bit (wdd) needs to be writ ten twice, i.e., with two consecutive spi words in order to be altered to '1'. in order to disable the watchdog right from the start (i.e., a fter external power-up or after sleep mode), pin vdiv has to be tied to vcc until the startup time t reset of typ. 4ms has elapsed (see section 3.14 ?vdiv input/ output pin? on page 7 ). the minimum time for the first watchdog pulse is required afte r the undervoltage reset at nres disappears. it is defined as lead time t d . after wake-up from sleep mode, the lead time t d starts with the positive edge of the nres output. 10.1 typical timing sequence with r wd_osc = 51k the trigger signal t wd is adjustable between 20ms and 64ms using the external resistor r wd_osc . for example, with an ex ternal resistor of r wd_osc = 51k 1%, the typical parameters of the watchdog are as follows. t osc = 0.782 r wd_osc + 1.7 10 -6 (r wd_osc ) 2 [r wd_osc in k ; t osc in s] t osc = 39.9s due to 51k t d = 3948 39.9s = 157.5ms t 1 = 553 39.9s = 22.1ms t 2 = 527 39.9s = 21ms t nres = constant = 4ms after ramping up the battery voltage, th e vcc regulator is switched on. the reset output nres stays low for the time t reset (typically 4ms), then it switc hes to high, and the watchdog waits for the trigge r sequence from the microcontroller. the lead time, t d , follows the reset and t d = 155ms. in this time, the first watchdog puls e from the microcontroller is required. if the trigger pulse ntrig occurs during this time, the time t 1 starts immediately. if no trigger signal occurs during the time t d , a watchdog reset with t reset = 4ms resets the mi crocontroller after t d = 155ms. the times t 1 and t 2 have a fixed relationship. a triggering signal from the micr ocontroller is anticipated wi thin the time frame of t 2 = 21.6ms. to avoid false triggering from glitches, the trigger pulse must be longer than t trig,min > 7s. this slope restarts the watchdog sequence. if the triggering signal fails in this open window t 2 , the nres output is drawn to ground. a triggering signal during the closed window t 1 immediately switch es nres to low.
29 ata664151 [datasheet] 9268h?auto?08/14 figure 10-1. timing sequence with r wd_osc = 51k 10.2 worst case calculation with r wd_osc = 51k the internal oscillator has a tole rance of 20%. this means that t 1 and t 2 can also vary by 20%. the worst-case calculation for the watchdog period t wd is as follows. the ideal watchdog time t wd is between the maximum t 1 and the minimum t 1 plus the minimum t 2 . t 1,min = 0.8 t 1 = 16.8ms, t 1,max = 1.2 t 1 = 25.2ms t 2,min = 0.8 t 2 = 17.7ms, t 2,max = 1.2 t 2 = 26.5ms t wdmax = t 1min + t 2min = 16.8ms + 17.7ms = 34.5ms t wdmin = t 1max = 25.2ms t wd = 29.9ms 4.6ms (15%) a microcontroller with an oscillator tolerance of 15% is sufficient to supply the trigger inputs correctly. note that in the case of a missing or shorted resistor on pin wdosc, the watchdog oscillator period will be well below or above the reachable values listed above. in other words, if not disabled after startup by using the vdiv pin or during operation with the spi configuration, a watchdog reset will be generated all the time for fail-safe reasons. t nres = 4ms undervoltage reset watchdog reset t reset = 4ms t trig > 7s t 1 = 20.6ms t 2 = 21ms t 2 t 1 t wd t d = 155ms vcc 5v ntrig nres table 10-1. typical watchdog timings r wd_osc k oscillator period t osc /s lead time t d /ms closed window t 1 /ms open window t 2 /ms trigger period from microcontroller t wd /ms reset time t nres /ms 34 26.6 105 14.0 14.7 20.13 4 51 39.9 157.5 21 22.1 29.85 4 91 71.2 281 37.5 39.4 53.27 4 120 93.9 370.6 49.5 51.9 70.26 4
ata664151 [datasheet] 9268h?auto?08/14 30 11. cl15 hv input the cl15 pin can be used as ignition state detection and wake-up input. it has a weak internal pull-down structure, so if no voltage is connected to this pin, it is at ground level, the passive state of this input. in order to generate an interrupt req uest or to wake-up from sleep mode, a certain voltage needs to be applied to this pin. the input voltage threshold can be adjusted by varyin g the external resistor due to the input current i cl_15 . to protect this pin against voltage transients, a serial resistor of 10k and a ceramic capacitor of 47nf are recommended. with this rc combination you can increase the wake-up time t cl15deb as well as enhance sensitivity agai nst transients when ignition of the cl15 pin occurs. you can also increase the wake-up time using external capacitors with higher values. in figure 11-1 , the reaction of the atmel ? ata664151 to a signal at the cl15 pin is shown. note that the pin is connected via an r/c low-pass filter. figure 11-1. timing for cl15 debouncing in the diagram above, the voltage at the cl15 pin is shown. du e to the r/c filter, the voltage does not immediately increase but instead slowly over time. as s oon as the voltage exceeds approximat ely 3v, the internal debouncing time t cl15deb starts. after this elapses, a wake-up is indica ted by a falling edge on the nirq pin. 12. fail-safe features during a short-circuit at lin to v battery , the output current is limited to i bus_lim . due to power dissipation, the chip temperature might exceed t linoff , causing a shutdown of the lin output transistor. that in turn starts the chip cooling phase, and after a hysteresis of t hys the output can be switched on agai n with txd = 0. during shutdown, rxd indicates the lin bus state, which is typically recessive bec ause the output transistor is off. please note that the vcc voltage regulator works independently from the lin output tr ansistor temperature monitor because it is equipped with its own monitor. during a short-circuit at lin to gnd, the ic can be swit ched to sleep mode. if the short-circuit disappears, the ic starts with a remote wake-up. the reverse current is very low < 2 a at the lin pin during loss of v batt . this is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. during a short circuit at vcc, the ou tput limits the output current to i vcclim . because of undervoltage, nres switches to low and can therefore reset the conn ected microcontroller. if the chip tem perature of the vcc output transistor exceeds the value t vccoff , the vcc output switches off. the chip cools down and after a hysteresis of t hys , the output is reactivated. the ncs pin provides a pull-up resistor to force th e spi output into tri-state mode if ncs is disconnected the txd pin provides a pull-up resistor to force the tran sceiver into recessive mode if txd is disconnected. if the wdosc pin has a short-circuit to gnd or the resistor is disconnected, the watchdog runs with an internal oscillator and ensures a reset takes place. if there is no ntrig signal and short circuit at wdosc, the nres swit ches to low after t wdofshi . for an open circuit (no resistor) at wdosc it switches to low after t wdofslo . the watchdog disable bit wdd in the configuration register needs to be written twice in order to take effect. this avoids unwanted watchdog shutdowns due to data misinterpretation caused by emi. if the iref pin has a short-circuit to gnd or the resistor is disconnected/shorted to vcc, the current sources run with an internal reference current which guarante es basic functionality of the application. cl15 nirq cl15_int t rc t cl15deb
31 ata664151 [datasheet] 9268h?auto?08/14 13. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit maximum voltage on supply pin vs 1) v sup,stby ?0.4 +40 v operating supply voltage (load dump) pulse time 500ms t a = 25c vcc output current i vcc 50ma 1) v sup,ldump +40 v operating supply voltage (jump start) pulse time 2min t a = 25c output current i vcc 50ma 1) v sup,jstart 27 v voltage levels on pins - cs1-8 - cl15 (with 10k /47nf) -> dc voltage 1) -> transient voltage due to iso7637 (coupling via 1nf) ?2 ?150 +40 +100 v v voltage levels on pins 1) - lin - vbatt (with 51 /10nf) -> dc voltage ?27 +40 v voltage levels on logic/low-voltage pins: rxd, txd, nres, ntrig, wdosc, pwmy, vdiv, ncs, sck, mosi, miso ?0.4 v vcc + 0.4v v voltage levels on pin vcc v vcc ?0.4 +5.5 v esd according to ibee lin emc test spec. 1.0 following iec 61000-4-2 - pin vs (100nf) to gnd - pin lin (220pf) to gnd - pin cl15 (10k , 47nf) to gnd - pin vbatt (10nf) to gnd - pins csx (10nf) to gnd 6 kv hbm esd according to ansi/esd-stm5.1 jesd22-a114 aec-q100 (002) mil-std-883 (m3015.7) 2 kv cdm esd according to stm 5.3.1 750 v mm esd according to eia/jesd22-a115 esd stm5.2 aec-q100 (002) 200 v note: 1. voltage between any of following pins must not exceed 40v: vs, vbatt, cl15, csx, lin
ata664151 [datasheet] 9268h?auto?08/14 32 esd hbm following stm5.1 with 1.5k , 150pf - pins vs, lin, cl15 to gnd 8 kv junction temperature t j ?40 +150 c storage temperature t s ?55 +150 c 13. absolute maximum ratings (continued) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit note: 1. voltage between any of following pins must not exceed 40v: vs, vbatt, cl15, csx, lin 14. thermal characteristics parameters symbol min. typ. max. unit thermal resistance ju nction to heat slug r thjc 10 k/w thermal resistance junction to ambient, where heat slug is soldered to pcb according to jedec r thja 35 k/w thermal prewarning threshold of vcc regulator temperature monitor t vccprew 120 140 c thermal shutdown threshold of all temperature monitors t jsd 150 165 185 c thermal shutdown hysteresis t jsdhyst 10 17 25 k
33 ata664151 [datasheet] 9268h?auto?08/14 15. electrical characteristics 5v < v s < 27v, ?40c < t j < 150c, chip configuration as default, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* 1 vs pin 1.1 nominal dc voltage range for full operation vs v s 5 27 v b 1.2 supply current in sleep mode v lin > v s ? 0.5v v s 14v (t j = 25c) vs i vssleep 4 8 12 a b v lin > v s ? 0.5v v s 14v (t j = 125c) vs i vssleep 4 11 18 a a sleep mode bus shorted to gnd vs i vssleep_short 20 35 a a 1.3 supply current in active low-power mode, all peripherals off v lin > v s ? 0.5v v s 14v (t j = 25c) without load at vcc vs i vsact_lp 33 45 a b v lin > v s ? 0.5v v s 14v (t j = 125c) without load at vcc vs i vsact_lpt 40 55 a a lin-bus shorted to gnd vs i vsact_lp_short 55 80 a b 1.4 supply current in active mode after startup (wd active), no vcc load v lin > v s ? 0.5v v vs 14v vs i vsact_wd 120 200 a a 1.5 supply current in active mode after startup (wd active), high vcc load bus recessive v vs = 14v i vcc = ?45ma vs i vsdom 45.1 46 ma a 1.10 supply current in different active modes bus recessive v vs = 14v i vcc = 0 r_iref = 5.6k vs i vsact_wd i vsact_lin i vsact_cs i vsact_vdiv 185 300 2600 300 a d 1.7 vs undervoltage thresholds status bit vss = 1 vs v vsthu 4.0 4.4 v a status bit vss = 0 vs v vstho 4.3 4.95 v a 1.8 vs undervoltage threshold hysteresis v vstho ? v vsthu vs v vsth_hyst 0.19 0.4 0.65 v a 1.9 minimum vs operation voltage vcc active, spi operational vs v vsopmin 3.8 v a 2 rxd output pin 2.1 low-level output sink capability i rxd =2ma rxd v rxdsink 0.4 v a 2.2 high-level output source capability i rxd = ?2ma rxd v rxdsource v vcc ? 0.4v v a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata664151 [datasheet] 9268h?auto?08/14 34 3 txd input pin 3.1 maximum voltage level for logic ?low? txd v txdl,max 0.33 x v vcc v a 3.2 minimum voltage-level for logic ?high? txd v txdh,min 0.66 x v vcc v a 3.3 pull-up resistor v txd = 0v, v vcc = 5v txd r txd 40 90 140 k a 3.4 input leakage current v txd =v vcc txd i txdleakh +1 a a 4 nirq output pin (open drain) 4.1 low-level output sink capability i irq = 2ma nirq v irqsink 0.4 v a 4.2 high-level input leakage current v nirq = v vcc nirq i nirqleak,h 1 a a 4.3 nirq pin pull-up resistor value v nirq = 0v nirq r nirq 60 100 200 k a 5 ntrig watchdog input pin 5.1 maximum voltage level for logic ?low? ntrig v ntrigl,max 0.33 v vcc v a 5.2 minimum voltage-level for logic ?high? ntrig v ntrigh,min 0.66 v vcc v a 5.3 pull-up resistor v ntrig = 0v, v vcc = 5v ntrig r ntrig 40 90 140 k a 5.4 input leakage current v ntrig = v cc ntrig i ntrigleakh +1 a a 5.5 minimum ntrig pulse width for watchdog trigger ntrig t trig 7 s b 7 lin-bus driver 7.1 driver recessive output voltage external lin pull-up 1k lin v busrec 0.9 v s v s v b 7.2 driver dominant voltage v vs = 7v r bus = 500 lin v buslosup, max 1.2 v a 7.3 driver dominant voltage v vs = 18v r bus = 500 lin v bushisup,ma x 2 v a 7.4 driver dominant voltage v vs = 7.0v r load = 1000 lin v buslosup,mi n 0.6 v a 7.5 driver dominant voltage v vs = 18v r load = 1000 lin v bushisup,min 0.8 v a 7.6 internal pull-up resistor to vs resistor has a serial rectifier diode lin r lin 20 30 47 k a 7.7 voltage drop at the serial diodes in pull-up path with r slave i serdiode = 10ma lin v serdiode 0.4 1.0 v d 7.8 lin current limitation v bus = v batt_max lin i bus_lim 70 120 200 ma a 15. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c, chip configuration as default, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
35 ata664151 [datasheet] 9268h?auto?08/14 7.9 leakage current at loss of ground (1) module-gnd disconnected v s = v bat = 0v v lin = ?18v lin i bus_no_gnd ?20 +20 a a 7.10 leakage current at loss of battery (1) battery disconnected v s = v bat = 0v 0v v lin 18v lin i bus_no_vs 2 a a note: 1. bus communication must not be affected if the module gets disconnected from ground or from battery. parameters 7.9 and 7.10 cover these lin specification topics. 8 lin bus receiver 8.1 center of receiver threshold v bus_cnt = (v th_dom + v th_rec )/2 7v v s 27v lin v bus_cnt 0.475 v s 0.5 v s 0.525 v s v a 8.2 maximum allowed bus voltage to be detected as dominant state by receiver lin v bus_dom,max 0.4 v s v a 8.3 minimum allowed bus voltage to be detected as recessive state by receiver lin v busr_ec,min 0.6 v s v a 8.4 receiver input hysteresis v hys = v th_rec ? v th_dom lin v bus_hys 0.028 v s 0.1 v s 0.175 v s v a 8.5 dominant state receiver input current input leakage current driver off v bus = 0v v s = 12v lin i bus_pas_dom ?1 ?0.35 ?0.2 ma a 8.6 recessive state receiver input current driver off (recessive state) v batt = 18v v bus = 18v v bus = 40v lin i bus_pas_rec1 i bus_pas_rec2 11 25 a b a 8.7 lin pre-wake detection high-level input voltage lin v lin_preh v s ? 2v v s + 0.3v v a 8.8 lin pre-wake detection low-level input voltage activates the lin receiver lin v lin_prel ?27 v s ? 3.3v v a 8.9 lin receiver enabling time time between rising edge on ncs and receiver ready rxd t rxdinvalid 15 s d 9 internal timers 9.1 dominant time for wake- up via lin-bus v lin = 0v lin t bus 70 90 150 s b 9.2 time delay for lin trx enable from active mode via spi delta between ncs high and txd/rxd transparent csn rxd t norm 2.5 10 s d 15. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c, chip configuration as default, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata664151 [datasheet] 9268h?auto?08/14 36 9.3 time delay for mode change from active mode to sleep mode via spi delta between ncs high and lin-trx offline csn rxd t sleep 2.5 10 s d 9.4 txd dominant time-out timer txd t dom 30 40 56 ms b 9.5 time delay for mode change from active low- power mode into normal mode via spi delta between csn high and txd/rxd transparent csn rxd t s_n 2.5 6 15 s d 9.11 txd time-out timer release time time for which txd must be at least at high level after a dominant state time-out txd t torel 10 s b 9.12 monitoring time for wake-up via lin bus lin t mon 8 14 ms a lin-bus driver ac parameters with different bus loads load 1 (small): 1nf, 1k load 2 (large): 10nf, 500 ; c rxd = 20pf; load 3 (medium): 6.8nf, 660 characterized on samples; 9.6 and 9.7 specif ies the timing parameters for proper operation of 20kbit/s, 9.8 and 9.9 at 10.4kbit/s 9.6 duty cycle 1 th rec(max) = 0.744 v s th dom(max) = 0.581 v s v s = 7v to 18v t bit = 50s d1 = t bus_rec(min) /(2 t bit ) lin d1 0.396 b 9.7 duty cycle 2 th rec(min) = 0.422 v s th dom(min) = 0.284 v s v s = 7.6v to 18v t bit = 50s d2 = t bus_rec(max) /(2 t bit ) lin d2 0.581 b 9.8 duty cycle 3 th rec(max) = 0.778 v s th dom(max) = 0.616 v s v s = 7.0v to 18v t bit = 96s d3 = t bus_rec(min) /(2 t bit ) lin d3 0.417 b 9.9 duty cycle 4 th rec(min) = 0.389 v s th dom(min) = 0.251 v s v s = 7.6v to 18v t bit = 96s d4 = t bus_rec(max) /(2 t bit ) lin d4 0.590 b 9.10 slope time falling and rising edge at lin v s = 7v lin t slope_fall t slope_rise 3.5 22.5 s a 15. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c, chip configuration as default, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
37 ata664151 [datasheet] 9268h?auto?08/14 10 receiver electrical ac parameters of the lin physical layer lin receiver, rxd load conditions (c rxd ): 20pf 10.1 max propagation delay of receiver v s = 7.0v to 18v t rx_pd = max(t rx_pdrise , t rx_pdfall ) rxd t rx_pd 6 s a 10.2 symmetry of receiver propagation delay rising edge minus falling edge v s = 7.0v to 18v t rx_sym = t rx_pdr ? t rx_pdf rxd t rx_sym ?2 +2 s a 11 nres open drain output pin 11.1 low-level output sink capability i nres = 2ma nres v nressink 0.4 v a 11.2 low-level at low vcc v vcc = 2.5v i nres = 500a nres v nresll 0.4 v a 11.3 vcc power-up reset time v s 5.5v c nres = 20pf nres t uvreset 2 4 6 ms b 11.4 reset debounce time for falling edge at vcc v s 5.5v c nres = 20pf nres t nresfall 1.5 10 s a 11.5 high level input leakage current v nres = v vcc nres i nresleakh 1 a a 11.6 nres pin pull-up resistor value v nres = 0 nres r nres 60 100 200 k a 12 watchdog oscillator 12.1 voltage at wdosc in active mode, wdo enabled 34k r wdosc 120k v vs 4v wdosc v wdosc 1.13 1.23 1.33 v a 12.2 wdosc load regulation dv wdosc = v wdosc,34k ? v wdosc,120k wdosc dv wdosc ?20 +20 mv a 12.3 oscillator period r osc = 34k t wdosc,low 21.3 26.6 31.9 s a 12.4 oscillator period r osc = 120k t wdosc,hi 75.1 93.9 102 s a 12.5 watchdog oscillator fail-safe periods wdosc = 0v wdosc = open t wdofshi t wdofslo 4.5 104 18 200 s d 13 watchdog window and reset timing 13.1 watchdog lead time after reset cycles are relative to t wdosc t wdlead 3948 cycles b 13.2 watchdog closed window cycles are relative to t wdosc t wdclose 527 cycles b 13.3 watchdog open window cycles are relative to t wdosc t wdopen 553 cycles b 13.4 watchdog reset time nres nres t wdnres 3 4 6 ms b 15. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c, chip configuration as default, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata664151 [datasheet] 9268h?auto?08/14 38 14 cl15 pin 14.1 high-level input voltage threshold spi status bit ?cl15s? readback as ?1? cl15 v cl15h 4.5 v a 14.2 low-level input voltage threshold spi status bit ?cl15s? readback as ?0? cl15 v cl15l 2 v a 14.3 cl15 pull-down current v s 27v v cl15 = 27v cl15 i cl15 50 100 a a 14.4 internal debounce time without extern al capacitor cl15 t cl15deb 80 160 250 s b 14.5 hysteresis of input voltage comparator v cl15h ? v cl15l cl15 v cl15hsyt 0.5 1 1.5 v a 17 vcc voltage regulator in active mode 17.1 output voltage vcc 5.5v < v s < 18v (0ma to 50ma) vcc v vccnor 4.9 5.1 v a 6.5v < v s < 18v (0ma to 80ma) vcc v vccnor 4.9 5.1 v c 17.2 output voltage vcc at low vs 3v < v s < 5.5v vcc v vcclow 2.3 5.1 v a 17.3 regulator drop voltage for medium load v s > 4v i vcc = ?20ma v vccdrop = v vs ? v vcc vs, vcc v vccdrop1 250 mv a 17.4 regulator drop voltage for high load v s > 4v i vcc = ?50ma v vccdrop = v vs ? v vcc vs, vcc v vccdrop2 400 600 mv a 17.6 line regulation 5.5v < v s < 18v vcc vcc line 0,8 % b 17.7 load regulation 5ma < i vcc < 50ma 100khz vcc vcc load 0.2 0.8 % b 17.8 output current limitation vs > 5.5v vcc i vcclim ?240 ?120 -80 ma a 17.9 external load capacity esr < 5 at f = 100khz vcc v thunn 1.8 2.2 f d 17.10 vcc undervoltage threshold referred to vcc v s > 5.5v vcc v vccuv 2.7 3.1 v a 17.11 hysteresis of undervoltage threshold referred to vcc v s > 5.5v vcc v vccuv_hys 190 300 400 mv a 17.12 ramp-up time v s > 5.5v to v cc = 5v c vcc = 2.2f i load = ?5ma at vcc vcc t vcc 400 700 s a 18 battery voltage divider 18.1 divider ratio vdiv r div_5v 1 : 4 d 18.2 divider precision v vbatt = 6 to 19v vdiv p vbatt ?2 +2 % a 18.3 divider resistance v vbatt = 12v vbatt r vbatt 44 120 k a 18.4 input leakage current with disabled divider v vbatt 27v vbatt i vbattleak 0.1 1 a a 15. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c, chip configuration as default, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
39 ata664151 [datasheet] 9268h?auto?08/14 19 lin driver in high-speed mode (all tests using r lin = 500 , c lin = 600pf) 19.1 transmission bit rate v vs = 7v to 18v lin sp 200 kbit/s c 19.2 slope time lin falling edge v vs = 7v to 18v lin t hsslope_fall 0.3 1 2 s a 19.3 slope time lin rising edge, depending on rc-load v vs = 7v to 18v lin t hsslope_rise 0.5 2 3 s a 20 switch interface un it (cs1-8, iref) 20.1 maximum highside output current v vs ? v csx 2.6v v vs 7v i iref = ?300a csx i csx,maxh ?35 ?20 ma a 20.2 maximum lowside output current v csx 2.6v v vs 7v i iref = ?300a csx i csx,maxl 20 35 ma a 20.3 current source multiplier from reference current i iref , imul=100 v vs 7v v csx,hs = v vs ? 2.6v i iref = ?200a csx ri cs_h 95 100 105 a 20.4 current source multiplier from reference current i iref , imul=50 v vs 7v v csx,hs = v vs ? 2.6v i iref = ?200a csx ri cs_l 47.5 50 52.5 a 20.5 switch input comparator threshold csx v csxth 3.6 4.4 v a 20.6 switch input comparator hysteresis csx v csxhyst 200 300 500 mv a 20.7 current source rising voltage slope v vs = 14v i iref = 100a r csx = 1k 25% to 90% csx du csx,rise 0.7 8 v/s c 20.8 current source falling voltage slope v vs = 14v i iref = 100a v csx = 0v 90% to 25% csx du csx,fall 0.7 8 v/s c 20.22 current source rising voltage slope, slope control disabled v vs = 14v i iref = 10a r csx = 1k 25% to 90% csscd = 1 csx du csx0,risefast 6.5 22 v/s c 20.23 current source falling voltage slope, slope control disabled v vs = 14v i iref = 100a v csx = 0v 90% to 25% csscd = 1 csx du csx,fallfast 6.5 30 v/s c 15. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c, chip configuration as default, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata664151 [datasheet] 9268h?auto?08/14 40 20.9 output voltage on iref pin v vs 7v 10a i iref 250a at least one current source active iref v iref 1.19 1.23 1.27 v a 20.10 internally generated iref fail-safe current in case of open or shorted iref pin v iref = 0v i iref = 0a iref i ireffs 60 60 140 140 a a 20.11 switch input debouncing time time from voltage level change on pin csx to signal state change visible in spi register csx t csxdeb 2 13 s b 20.12 switch input leakage current current source and voltage divider off v csx = 0 v v csx = v vs csx i csx,leak ?3 +3 a a 20.13 current source enabling time v vs = 14v v csx =0v(h)/v csx = 14v(l) i iref = 100a test time until abs(i csx ) 9.5ma csx t csxon 3 10 s a 20.14 current source shutdown time v vs = 14v v csx =0v(h)/v csx = 14v(l) i iref = 100a test time until abs(i csx ) 0.5ma csx t csx,off 3 12 s a 20.15 voltage divider resistance v csx = 4v csx r csxdiv 50 95 150 k a 20.16 voltage divider precision v csx = 4v csx p csxdiv ?3 +3 % a 20.17 maximum current source switching frequency csx fcsx,max 20 khz d 20.18 maximum voltage level for logic ?low? pwm1..3 v pwml,max 0.33 v vcc a 20.19 minimum voltage-level for logic ?high? pwm1..3 v pwmh,min 0.66 v vcc a 20.20 pwm input leakage current, low level v pwmy = 0 pwm1..3 i pwmleakl ?1 a a 20.21 pwm input pull-down resistor value v pwmy = v vcc pwm1..3 r pwm 60 100 220 k a 15. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c, chip configuration as default, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
41 ata664151 [datasheet] 9268h?auto?08/14 21 serial programming interface and control logic (spi) 21.1 maximum input clock frequency f spi = 1/t sck c_miso 140pf (external) sck f spi,max 4 mhz d 21.2 maximum input signal low level threshold mosi sck ncs v spil,max 0.33 x v vcc v a 21.3 minimum input signal high level threshold mosi sck ncs v spih,min 0.66 x v vcc v a 21.4 input pin leakage current v mosi = v sck = v ncs = v vcc v mosi = v sck = 0 mosi sck ncs mosi sck i leak,h i leakl ?1 ?1 +1 +1 +1 a a 21.5 ncs pin pull-up resistor v ncs = 0; v vcc = 5v ncs r ncs 60 120 200 k a 21.6 output low level sink capability i miso = 2ma miso v misosink 0.4 v a 21.7 output high level source capability i miso = ?2ma miso v misosource v vcc ? 0.4 v a 21.8 miso pin tristate input leakage current v ncs = v vcc v miso = v vcc /2 miso i misoleak ?1 +1 a a 21.9 chip select minimum setup time (-> earliest time to start clocking) ncs t spisetup,min 250 ns d 21.10 chip select minimum hold time (-> earliest time after clocking to release chip select) ncs t spihold,min 250 ns d 21.11 minimum spi data evaluation time (-> minimum time between positive and negative edge of chip select) ncs t spieval,min 8 14 s d 21.12 interrupt triggering delay nirq t nirqtrig 2 7 s b 21.13 spi clock duty cycle limits t sck_h /t sck sck d sck 0.4 0.6 d 21.14 propagation delay from spi clock to miso data output c_miso 140pf (external) sck miso t clk2data 10 120 ns a 15. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c, chip configuration as default, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata664151 [datasheet] 9268h?auto?08/14 42 16. application information figure 16-1. definition of bus timing characteristics txd (input to transmitting node) vs (transceiver supply of transmitting node) rxd (output of receiving node1) rxd (output of receiving node2) lin bus signal thresholds of receiving node1 thresholds of receiving node2 t bus_rec(max) t rx_pdr(1) t rx_pdf(2) t rx_pdr(2) t rx_pdf(1) t bus_dom(min) t bus_dom(max) th rec(max) th dom(max) th rec(min) th dom(min) t bus_rec(min) t bit t bit t bit
43 ata664151 [datasheet] 9268h?auto?08/14 figure 16-2. application example 1: lin slave with different external circuitry at the csx-pins txd ntrig rxd agnd vcc vs cs8 cs7 cs6 cs5 cs2 cs1 iref vdiv wdosc pwm3 pwm2 pwm1 nres nirq miso mosi sck ncs cs4 32 1 8 24 16 gnd gnd-lin lin gnd vbatt cl15 cs3 atmel ata664151 qfn32 5mm x 5mm 10k 10k 10k 12k 51k vs lin vs 51 10nf 47nf 100nf 2.2f 22f 100nf + + 10nf 220pf vba t vcc gnd microcontroller cl15 gnd debug (1) (1) note: if the watchdog shall be disabled directly after power-up (e.g. for microcontroller programming or debugging purposes) the pin vdiv must be tied to high level until the reset phase ends (positive slope at pin nres).
ata664151 [datasheet] 9268h?auto?08/14 44 figure 16-3. application example 2: lin slave for rgb-led-control txd ntrig rxd agnd vcc vs cs8 cs7 cs6 cs5 cs2 cs1 iref vdiv wdosc pwm3 pwm2 pwm1 nres nirq miso mosi sck ncs pwm1 pwm2 pwm3 cs4 32 1 8 24 16 gnd gnd-lin lin gnd vbatt cl15 cs3 atmel ata664151 qfn32 5mm x 5mm 10k 10k 12k 51k lin r g b 51 10nf 100nf 2.2f 22f 100nf + + 10nf 220pf vba t vcc gnd microcontroller gnd vs vs debug (1) (1) note: if the watchdog shall be disabled directly after power-up (e.g. for microcontroller programming or debugging purposes) the pin vdiv must be tied to high level until the reset phase ends (positive slope at pin nres).
45 ata664151 [datasheet] 9268h?auto?08/14 figure 16-4. application example 3: lin slave for h-bridge control of small dc-motors txd ntrig rxd agnd vcc vs cs8 cs7 cs6 cs5 cs2 cs1 iref vdiv wdosc pwm3 pwm2 pwm1 nres nirq miso mosi sck ncs cs4 32 1 8 24 16 gnd gnd-lin lin gnd vbatt cl15 cs3 atmel ata664151 qfn32 5mm x 5mm 10k 10k 51 5.6k 51k lin 10nf shunt vsh vsh 100nf 2.2f n1 (opt) n2 22f 100nf + + 10nf 220pf vbat vcc gnd microcontroller gnd p1 p2 m vs vs debug (1) (1) note: if the watchdog shall be disabled directly after power-up (e.g. for microcontroller programming or debugging purposes) the pin vdiv must be tied to high level until the reset phase ends (positive slope at pin nres).
ata664151 [datasheet] 9268h?auto?08/14 46 figure 16-5. application exampl e 4: lin slave relay driver txd ntrig rxd agnd vcc vs cs8 cs7 cs6 cs5 cs2 cs1 iref vdiv wdosc pwm3 pwm2 pwm1 nres nirq miso mosi sck ncs cs4 32 1 8 24 16 gnd gnd-lin lin gnd vbatt cl15 cs3 atmel ata664151 qfn32 5mm x 5mm 10k 10k 51 5.6k 51k lin 10nf 100nf 2.2f 22f 100nf + + 10nf 220pf vbat vcc gnd microcontroller gnd m debug (1) (1) note: if the watchdog shall be disabled directly after power-up (e.g. for microcontroller programming or debugging purposes) the pin vdiv must be tied to high level until the reset phase ends (positive slope at pin nres).
47 ata664151 [datasheet] 9268h?auto?08/14 18. package information 17. ordering information extended type number package remarks ata664151-wnqw qfn32 5x5mm v cc = 5v, voltage divider, v vccuv = 2.9v common dimensions (unit of measure = mm) package drawing contact: packagedrawings@atmel.com gpc symbol min nom max note 0.8 a 0.9 1 0.0 a1 0.02 0.05 0.15 a3 0.2 0.25 4.9 d 5 5.1 3.45 d2 3.6 3.75 4.9 e 5 5.1 3.45 e2 3.6 3.75 0.35 l 0.4 0.45 0.16 b 0.23 0.3 e 0.5 bsc drawing no. rev. title 6.543-5124.02-4 2 11/30/11 package: vqfn_5x5_32l exposed pad 3.6x3.6 dimensions in mm specifications according to din technical drawings top view partially plated surface d 1 8 32 pin 1 id e side view a3 a a1 b l z 10:1 bottom view e d2 9 1 8 16 17 24 25 32 e2 z two step singulation process
ata664151 [datasheet] 9268h?auto?08/14 48 19. errata 19.1 atmel ata664151 1. the current sources, pins cs1 to cs8, may show unexpec ted behavior when not initialized correctly thus resulting in small amounts of current to be provided. problem fix/workaround the current sources can be brought into a defined status by disabling the slope control for the cs-ports when initial- izing the device. this can be achieved using the spi bit c sscd. the slope control can be turned off 10s after it was enabled.
49 ata664151 [datasheet] 9268h?auto?08/14 20. revision history please note that the following page numbers re ferred to in this section re fer to the specific revision mentioned, not to this document. revision no. history 9268h-auto-08/14 ? put datasheet in the latest template 9268g-auto-12/13 ? section 13 ?absolute maximum ratings? on pages 31 to 32 updated 9268f-auto-07/13 ? section 13 ?absolute maximum ratings? on pages 31 to 32 updated ? section 14 ?thermal characteristics? on page 32 updated ? section 15 ?electrical characteristics? numbers 3.3, 5.3, 14.3, 20.3 , 20.4 and 20.16 on pages 33 to 41 updated 9268e-auto-07/13 ? section 10.1 ?typical timing sequence with r wd_osc = 51k ? on page 28 updated ? section 10.2 ?worst case calculation with r wd_osc = 51k ? on page 29 updated ? section 15 ?electrical characteristics? numbers 1. 7, 1.8, 1.9, 4.3, 11.6 , 13.1, 13.2, 13.3, 17.12, 18.3, 20.11, 20.13, 20.14, and 21.5 on pages 33 to 41 updated ? section 19 ?errata? on page 48 added 9268d-auto-11/12 ? section 3.12 ?ntrig input pin? on page 6 updated ? section 3.13 ?vbatt input pin? on page 6 updated ? section 3.16 ?cs1 to cs8 high-voltage input/output pins? on page 7 updated 9268c-auto-09/12 ? ata664131 and ata664154 removed ? section 17 ?ordering information? on page 47 updated 9268b-auto-05/12 ? section 15 ?electrical characteristics? num bers 20.7, 20.8, 20.22 and 20.23 on page 40 updated
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